Implementasi pada FPGA atas Soft-Output Viterbi Algorithm (SOVA) untuk Pengawasandian Turbo
Abstract
There are two kinds of algorithm that widely used for decoding the turbo codes, those are Soft-Output Viterbi Algorithm (SOVA) and Maximum A Posteriori Algorithm (MAP). MAP Algorithm gives a better result on error correcting capability, but the consequence it has higher complexity algorithm, in contrary to SOVA. This paper presented a design for decoding turbo codes using SOVA with Very high-speed integrated circuit Hardware Description Language (VHDL) as the modelling program and the design is implemented on the FPGA. Implementation result shows that SOVA occupies 159 slices or 3% of the available slices in Xilinx Spartan-3E, 105 flip flop (1%), 278 LUT (2%), and 141 IOB (60%) with maximum frequency clock is 43,384 MHz. FPGA implementation of SOVA decoder is able to correct up to six non-burst error symbols from 16 received symbols, but SOVA fails to perform its errorcorrecting capability for three consecutive error symbols. SOVA decoder can be implemented for turbo decoding by combining SOVA decoder with interleaver and deinterleaver.
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