Design of Direct Digital Synthesizer (DDS) Based on Field Programmable Gate Array (FPGA) for Electrical Impedance Tomography (EIT)

Abstract

Direct Digital Synthesizer (DDS) systems play a critical role in high-precision signal generation for applications like medical imaging and RF communications. This research explores the development of a DDS system using Field-Programmable Gate Array (FPGA) technology, with a focus on optimizing signal accuracy, resource efficiency, and signal-to-noise ratio (SNR). The study implemented two DDS designs on an FPGA: one based on the CORDIC algorithm and the other using a Look-Up Table (LUT) approach. Key components of the system included a phase accumulator, phase register, and frequency calculation algorithms. The system's performance was evaluated by measuring signal output accuracy and SNR, utilizing the ISL6961IAZ DAC and RF Transformers PWB2010LC for signal conversion and transmission. The results showed that the DDS achieved near-target frequencies, with outputs of 100.4 kHz for a target of 100 kHz and 498.8 kHz for a target of 500 kHz. The LUT-based design demonstrated superior signal fidelity, achieving an SNR of 106 dB compared to 92 dB for the CORDIC-based design. However, resource utilization analysis revealed a trade-off between logic efficiency and memory usage: the CORDIC design consumed 26% of logic elements and only 1% of memory, while the LUT-based design used 8% of logic elements and 77% of memory. These findings highlight the importance of balancing design choices based on application-specific requirements for precision, resource constraints, and performance.