Implementasi Rangkaian CRC (Cyclic Redundancy Check) Generator pada FPGA (Field Programmable Gate Array)

https://doi.org/10.22146/ijeis.43906

Nia Gella Augoestien(1*), Ryan Aditya(2)

(1) Departemen Ilmu Komputer dan Elektronika, FMIPA UGM, Yogyakarta
(2) KSB Indonesia
(*) Corresponding Author

Abstract


  Data integrity in high speed data transmission process is a major requerment that can not be ignored. High speed data transmission is prone to data errors. CRC (Cyclic Redundancy Check) is a mechanism that is often used as a detector errors in data transmission and storage process. When CRC is implemented using embedded software or processor, CRC requires many clock cycles. If CRC Generator implemented in special dedicated hardware, computational time reduced so that it can be met the high speed system communication requirement.

This paper propose the design and implementation of CRC generator on FPGA that capable to minimaze computational time. The method is to reduce calculation latency by separating the coefficients of certain digits and calculating directly the result of  polinomial key modulo.

CRC Generator in this paper was implemented on Xilinx Spartan®-6 Series (XC6LX16-CS324). The modeling results have succeeded  to finish computation on 1 clock cycle. Hardware eficiency is achieved 0.38 Gbps/Slice, while the throughput is 3,758 Gbps.


Keywords


High speed computation; single clock processing; Low latency

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References

[1]      Mitra, J. dan Nayak, T., 2017, Reconfigurable very high throughput low latency VLSI (FPGA) design architecture of CRC 32, The VLSI Journal, 56, pp. 1-14.[Online]. Available:https://www.sciencedirect.com/science/article/pii/S0167926016300669. [Accessed: 18-Maret-2018]

[2]      S. Panda and G. L. Kumar, "Comparison of serial data-input CRC and parallel data-input CRC design for CRC-8 ATM HEC employing MLFSR," 2014 International Conference on Electronics and Communication Systems (ICECS), Coimbatore, 2014, pp. 1-4. [Online].Available:http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6892739&isnumber=6892507. [Accessed: 10-Feb-2019]

[3]     C. E. Kennedy and M. Mozaffari-Kermani, "Generalized parallel CRC computation on FPGA," 2015 IEEE 28th Canadian Conference on Electrical and Computer Engineering (CCECE), Halifax, NS, 2015, pp. 107-113.[Online] Available : https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7129169 [Accessed : 20 Oktober 2018]

[4]      A. R. Buzdar, L. Sun, R. Kashif, M. W. Azhar and M. I. Khan, Cyclic Redundancy Checking (CRC) Accelerator for Embedded Processor Datapaths, “International J. of Advanced Computer Science and Applications, Vol 8, No. 2, pp 321- 325, 2017[Online]. Available:https://thesai.org/Downloads/Volume8No2/Paper_42-Cyclic_Redundancy_Checking_CRC_Accelerator.pdf. [Accessed: 14-Mare-2018]

[5]      Y. Jun, D. Jun, L. Na, G. Yixiong and D. Yin, "FPGA-based multi-channel CRC generator implementation," 2010 International Conference on E-Health Networking Digital Ecosystems and Technologies (EDT), Shenzhen, 2010, pp. 81-84. [Online]. Available:  http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5496514&isnumber=5496503. [Accessed: 08-April-2017]

[6]      G. Sowndharya and A. Vasuki, "Reducing bit error rate using CRC verification in turbo codes," 2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), Chennai, 2017, pp. 627-631. [Online]. Available: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8299834. [Accessed: 19-Oktober-2018]

[7]     M. F. Hasmi, dan A. G. Keskar, “An Optimized FPGA Implementation of CAN 2.0 Protocol Error Detection Circuitry, Indonesian Journal of Electrical Engineering and Computer Science, Vol. 6, No. 3, pp. 602-614. Jun. 2017 [Online]. Available: https://www.iaescore.com/journals/index.php/IJEECS/article/download/7398/6616. [Accessed: 02-April-2018]

[8]  S.N.V.P.Kumar, S. B. Jyothi, G. K. S. Tejaswi, FPGA Based Design Of Parallel CRCGeneration For High Speed Application, IJSRET (International Journal of Scientific Research Engineering & Technology, Vol 6, 3, pp 258- 264, Mar. 2017 [Online]. Available: http://www.ijsret.org/pdf/121757.pdf. [Accessed: 20-Maret-2018]          

[9]     Y. Huo, X. Li, W. Wang and D. Liu, "High performance table-based architecture for parallel CRC calculation," The 21st IEEE International Workshop on Local and Metropolitan Area Networks, Beijing, 2015, pp. 1-6. [Online]. Available: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7114717&isnumber=7114713.[Accessed: 08-April-2018]

[10]   S. Ghaznavi, C. Gebotys and R. Elbaz, "Efficient Technique for the FPGA Implementation of the AES MixColumns Transformation," 2009 International Conference on Reconfigurable Computing and FPGAs, Quintana Roo, 2009, pp. 219-224.[Online]. Available: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5382055&isnumber=5381991. [Accessed: 02-April-2018]



DOI: https://doi.org/10.22146/ijeis.43906

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